A signal transmission/reception circuit which transmits and receives data, in which a signal transmission side transmits data with the addition of error checking and correcting codes to the data and a signal reception side checks and corrects errors in the received data using the error checking and correcting codes, has been known (for example, see JP 62-501047 A (Patent Document 1)).
FIG. 24 shows an exemplary format of signals transmitted and received in a signal transmission/reception circuit. In this example, a 3-bit ECC (Error Checking and Correcting) code is added to a 4-bit word to thereby form a code word of 7 bits in total, and respective code words are transmitted and received in units of code words with use of seven signal lines. In this case, by using a hamming code as an ECC code, for example, a 1-bit error in a word can be corrected.
On the other hand, in a video signal transmission device which performs serial transmission by multiplexing digital sound signals with video signals, a technique of adding an error checking and correcting code to each predetermined number of pieces of data of a digital sound signal and then sorting the bits, has been known (for example, see JP 5-219488 A (Patent-Document 2)). Specifically, the video signal transmission device disclosed in Patent Document 2 performs writing on a bit-by-bit basis serially into a memory of m×n cells in a row direction, and then performs reading by changing the direction to a column direction.    Patent Document 1: JP 62-501047 A    Patent Document 2: JP 5-219488 A
When data is transmitted between LSIs, the probability of occurrence of errors due to simultaneous switching noise is higher than the probability of soft errors. Simultaneous switching noise is noise generated in a power supply line when a plurality of drivers are switched simultaneously in the same logical direction (for example, in a direction from 0 to 1). When simultaneous switching noise is generated in a power supply line, errors may occur simultaneously in a plurality of signal lines which are receiving power supply from the power supply line. As such, as shown in the signal format of FIG. 24, in a signal transmission/reception circuit in which an error checking and correcting code is added to each word to thereby generate a code word, and transmission is performed in units of code words, if simultaneous switching noise is generated, the probability that an uncorrectable error of 2 bits or more occurs in the same code word would be high.
Meanwhile, as disclosed in Patent Document 2, in the case of performing writing on a bit-by-bit basis serially into a memory of m×n cells in a line direction for a given number of code words, and then performing reading by changing the direction to a column direction, if “m” and “n” are set to be the same as the number of bits of a code word, the signal format as shown in FIG. 24 can be transmitted by being converted into the signal format as shown in FIG. 25. In the signal format of FIG. 25, as the number of bits transmitted at a given time is 1 bit in every code word, even if simultaneous switching noise is generated and an error occurs in every bit on the signal line, an error in each code word is mere 1 bit. As such, the error is correctable in every code word. However, in the signal format of FIG. 25, the entire bits of the same code word are transmitted via the same signal line. As such, if multiple errors occur in any one of the signal lines due to performance degradation caused by aging of an input/output buffer amplifier provided to each signal line, for example, the possibility that an uncorrectable error of 2 bits or more occurs in the same code word would be high.